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½²×ù£º  VLSI Design and Reconfigurable Architecture for Embedded Systems

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This talk has two parts. The first part is focused on VLSI technology that is a driving force that has enabled low-power high-performance wireless devices, such as smartphones and tablets. At the receiver end, it needs to detect the symbols from the received signals with noise. As case studies, a system-on-chip architecture for MIMO detector will be presented. A belief-propagation based receiver design for sparse channel will be also discussed. Another key area of communication systems is error correction coding that is to recover the data with corrupted bits. Low-density parity-check code (LDPC) is a complex but very powerful technique. VLSI design for high-throughput, rate-compatible LDPC decoders will be presented.

The second part of this talk is about a coarse-grained reconfigurable architecture namely SmartCell that is targeted for stream processing applications in embedded systems. It is 2D tiled architecture with 64 elements. The benchmark results show that SmartCell is about 4 times more energy efficient than FPGA and can achieve 20 times more throughput than DSP.

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